This invention relates to a memory device with skew-removed I/O structure, and more particularly to a memory device having multiple I/O pads, which is applicable to all sorts of memory devices and logic devices using a I/O pads of odd number such as devices having a parity bit.
FIG. 1 shows a connection scheme between an internal data line and I/O pads in a conventional memory device 10 having I/O pads of odd number, for example, 9 I/O pads I/O0-I/O8. An internal data line should be connected to all I/O pads I/O0-I/O8 so that internal data lines 12 of nine times as much as I/O pad number are required in case where the memory device 10 has nine I/O pads. Data buffers DB10 to DB18 are respective connected to the respective I/O pads I/O10-I/O18 so as to transfer data between the I/O pad and a memory cell array 11.
The connection scheme of FIG. 1 has disadvantage as follows. As a number of the internal data lines are increased, the dimension that the internal data lines are occupied in a memory device is continually increased so that the dimension of the memory device 10 becomes seriously increased. Because the internal data lines 12 should be connected to all I/O pads, the internal data lines 12 are long in length so that data processing performance becomes degraded. That is, there is very large skew between the central I/O pads, for example I/O3 to I/O5 and the peripheral I/O pads, for example I/O0 and I/O9 due to line delay of the internal data line 12.